1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for accelerating the transfer of data in a computer system utilizing multiple buses.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units designed and manufactured by Intel Corporation of Santa Clara, Calif., such buses have typically been designed as either an Industry Standard Architecture (ISA) bus or an Expanded Industry Standard Architecture (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. Each of these buses functions at a frequency of eight megahertz. The data transfer rates provided by these bus widths and operational frequencies have been found limiting so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds that more closely approximate the speed at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card for an output display device) are joined to this faster local bus. However, it is most desirable to be able to continue to utilize those components which were designed to operate with the older buses and which operate at a slower rate. In order to do this, the slower ISA or EISA bus is maintained in essentially unchanged form; and those components which are able to tolerate longer access times are associated with the slower bus. It is then necessary to provide arrangements by which data may be transferred between all of the computer system components. This requires complicated interfacing arrangements. Although the theory behind using a local bus is good, many local bus designs have created conflicts in accessing components which actually slow the operation of the computer.
Intel Corporation has designed a new local bus which may be used in a computer system including other buses such as an ISA bus or an EISA bus (which are hereinafter referred to broadly as secondary buses). This new local bus provides faster throughput of data for selected components of the system without the conflicts which arise using other local bus systems. This new bus is referred to as the "peripheral component interconnect" (PCI) bus. A computer system using this PCI bus includes in addition to the physical PCI bus a first bridge circuit which provides the interface and controls the transfer of data among the PCI bus, the central processing unit, and main memory. A second bridge circuit is also provided as an interface between and a control for the transfer of data between a secondary bus and the PCI bus. Thus, the arrangement is such that components on the PCI bus transfer data to and receive data from main memory through the first bridge which joins to the central processor and to the main memory; while components on the secondary bus transfer and receive data through the second bridge and through the PCI bus for transfers with components on the PCI bus, and through the first and second bridges and the PCI bus for transfers with the central processor and the main memory.
Various designs of secondary bridges have been proposed. Specific embodiments of such bridges are described in detail in a publication entitled 82420/82430 PCIset, ISA and EISA Bridges, 1993, Intel Corporation. The design of these bridges is complicated by various factors. For example, each of the PCI and secondary buses is designed with controlling rules of operation which must be adhered to in designing a bridge to connect the two disparate buses. The PCI bus has been designed as a thirty-two bit bus. The PCI bus joins to the central processing unit and main memory through the first bridge circuit which is designed to buffer transfers of data so that a faster processor need not slow to the speed of the bus in transferring data. Because of this buffering arrangement, it is a requirement that write operations on the PCI bus be completed before any read operation of memory is allowed so that the coherency of the buffered write data is maintained when a write operation is interrupted. This requires that write data stored in buffers in each of the first and second bridges be flushed to its destination before the read process can commence. For many other similar reasons, flushing the data buffers of the bridges is required.
One of the operations which requires buffer flushing is the generation of an interrupt. In most cases an interrupt is an indication that some device requires service; in other cases, an interrupt signals the end of a data transfer. Such an interrupt indicates that a presently-running operation is to be interrupted or ended and a new operation is to be initiated. In such a case, it is necessary that write data stored in the data buffers be written to destination addresses (flushed) before the interrupt is acknowledged and serviced. Historically, this has been accomplished by an assertion by a device of an interrupt to an interrupt controller. The interrupt controller historically used with Intel processors physically resides with the circuitry which controls the operations on the secondary bus. In the case of a system utilizing a PCI bus, this circuitry resides in the bridge between the two buses and utilizes control signals used by other operations on the PCI bus. The interrupt signal generated by the secondary bus master causes the interrupt controller to generate a signal which is transferred to the CPU to indicate that some device requires servicing. The CPU completes the specific operation in which it is involved and generates an interrupt acknowledge cycle on the PCI bus. Since the interrupt controller resides in the bridge and utilizes the same signaling paths used by other components situated in the bridge, it recognizes the interrupt acknowledge cycle and generates signals to alert the bridge that a buffer flush is necessary so that the bridge buffers can be flushed before the interrupt is begun. When the flush of the buffers in both the first and second bridge circuits has been completed, the interrupt controller sends an interrupt vector to the CPU. This vector contains the address in memory of the interrupt handler routine for highest priority interrupt existing at the time the interrupt vector is sent. The CPU accesses the interrupt handler routine and services the interrupt.
However, a new interrupt controller called the Advanced Programmable Interrupt Controller (APIC) has been designed by Intel Corporation and is now being included in some systems which utilize a PCI bus. This new controller has various advanced abilities including the ability to provide programmable levels of interrupts, to handle both hardware and software interrupts, and to transfer interrupts among multiple processors. The APIC controller polls its input lines and generates an interrupt which is sent directly to the central processing unit. To accomplish this, the APIC controller is closely associated with the central processing unit rather than with the secondary bus controller circuitry. An APIC interrupt controller utilizes its own busing paths to transfer control signals. These busing paths are separate from those used by other circuitry associated with the PCI bus. Consequently, when the CPU responds to an APIC interrupt, there is often no signal present in the normal bridge control paths to alert the bridge circuitry that a flush is necessary. However, the APIC interrupt controller and the CPU must still cause the bridges to be flushed before the acknowledgment of the interrupt and the subsequent transfer of the interrupt vector to the CPU may be accomplished.
More importantly, a secondary bus master which has access to the secondary bus when an interrupt occurs cannot be forced to relinquish its ownership of the secondary bus until its operation is complete. Even so, it is sometimes necessary to interrupt the operations of such a bus master directed to the PCI bus and to read from memory as it exists at the time of the interrupt. This means that the data in buffers at the instant the interrupt occurs should be flushed to its ultimate destination. On the other hand, if a secondary bus master is transferring data through the bridge buffers to the PCI bus, the fact that the secondary bus master must wait for the PCI bus does not stop the transfer of data to the bridge buffers. In fact, it may continue to load these buffers after the interrupt occurs so long as buffer space exists and may require a substantial period before it completes its operations. Continuing the buffer filling is desirable since it helps maintain a higher data transfer rate on the secondary bus. Therefore, in order to improve performance of the APIC controller without affecting the optimized secondary bus performance due to the buffering scheme, it is desirable to flush only those buffers which include data written before the interrupt was generated. It is also desirable to flush those buffers as soon as possible so that an interrupt can be acknowledged and serviced. Consequently, it is necessary to provide some means of ascertaining which buffers were filled at the point an APIC interrupt was generated.